The present specification relates generally to fabrication processes for integrated circuits (ICs). More specifically, the present specification relates to a system for and method of patterning a layer of copper on a layer of material.
The semiconductor industry desires to manufacture integrated circuits (ICs) with higher and higher densities of devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This desire for large-scale integration has led to a continued shrinking of the circuit dimensions and features of the devices.
The ability to reduce the size of structures such as shorter gate lengths in field-effect transistors is driven by lithographic technology which is, in turn, dependent upon the wavelength of light used to expose the photoresist. In current commercial fabrication processes, optical devices expose the photoresist using light having a wavelength of 248 nm (nanometers). Research and development laboratories are experimenting with the 193 nm wavelength to reduce the size of structures. Further, advanced lithographic technologies are being developed that utilize radiation having a wavelength of 157 nm and even shorter wavelengths, such as those used in Extreme Ultra-Violet (EUV) lithography (e.g., 13 nm).
One challenge facing lithographic technology is fabricating features below 100 nm. Although photolithography is the most widely used technology in IC fabrication, other fabrication technologies are being explored. One such technology is xe2x80x9csoft lithographyxe2x80x9d, which is a non-photolithographic strategy based on such techniques as self-assembly, replica molding, and stamping. Examples are provided in U.S. Pat. No. 5,512,131 (Kumar et al.), U.S. Pat No. 5,900,160 (Whitesides et al.), and U.S. Pat. No. 6,060,121 (Hidber et al.), and also in Xia, Y. and Whitesides, G., xe2x80x9cSoft Lithographyxe2x80x9d, Annu. Rev. Mater. Sci. 1998, 28:153-84.
As explained by Xia and Whitesides, soft lithography utilizes an elastomeric block or stamp with patterned relief structures on its surface. The elastomeric block is cast molded, coated with a self-assembled monolayer (SAM), then printed onto a suitable medium, such as Au or Ag. A thin monolayer of material having a desired chemical property results. Soft lithography has been proposed for such applications as microcontact printing of SAMs, patterned SAMs as resists in selective wet etching, patterned SAMs as templates in selective deposition, micromolding, and related techniques.
One area of lithography which requires further development is the area of interconnects. As device sizes continue to decrease, the reduction in interconnect size has remained an obstacle.
Accordingly, what is needed is an improved system for and method of patterning a layer of copper on a material surface. Further, what is needed is a system for and method of patterning copper interconnects on an integrated circuit. Further still, what is needed is an interconnect fabrication process for providing interconnects having a smaller thickness. Further yet, what is needed is an elastomer stamper suitable for use in an interconnect stamping process.
The teachings hereinbelow extend to those embodiments which fall within the scope of the appended claims, regardless of whether they accomplish one or more of the above-mentioned needs.
According to an exemplary embodiment, a method of patterning a layer of copper on a material surface is provided. The method includes providing a stamp having a base and a stamping surface. The stamping surface defines a pattern. The method also includes providing a copper plating catalyst on the stamping surface; applying the stamping surface to the material surface. A pattern of copper plating catalyst is applied to the material surface. The method further includes providing a copper solution over the copper plating catalyst. A layer of copper is patterned on the material surface according to the method.
According to another exemplary embodiment, a method of fabricating copper interconnects on an integrated circuit is provided. The method includes stamping a predetermined pattern of copper plating catalyst on a layer of the integrated circuit and providing a copper solution over the copper plating catalyst. Copper interconnects are fabricated on the layer according to the method.
According to yet another exemplary embodiment, a method of making a stamp for an integrated circuit fabrication process is provided. The method includes providing a substrate, applying first and second layers of material on the substrate, forming a first aperture in the first layer of material, forming a second aperture in the second layer of material through the first aperture, and etching the substrate through the first and second apertures to form grooves in the substrates. The method also includes filling the grooves with an elastomer and allowing the elastomer to harden.